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PolytypeGuard: SiC Anneal-Window Planner

A web-based kinetics calculator for silicon carbide process engineers: enter an anneal temperature and dwell time, and it uses the published activation energies for stacking-fault nucleation (1.5 eV) and partial-dislocation expansion (0.54 eV) in the 3C-to-6H polytypic transition to compute a safe process window before unwanted polytype conversion takes hold.

Materials Science Information SystemsSilicon carbide power semiconductor manufacturing (substrate growth and high-temperature anneal process engineering)

Concept

PolytypeGuard is a focused planning tool for engineers running high-temperature steps in silicon carbide (SiC) substrate growth and device processing. The user enters a target temperature (e.g., 1800–2300 °C) and planned dwell time; the tool runs the two-step 3C→6H transition kinetics — fast nucleation of stacking faults (Ea = 1.5 eV) and slow expansion of partial dislocations (Ea = 0.54 eV) — through the Arrhenius equation and returns: (1) a nucleation-rate vs. expansion-rate chart across temperature, (2) the maximum dwell time before fault expansion exceeds a user-set tolerance, and (3) a side-by-side comparison of candidate anneal schedules. Pre-exponential factors are calibrated once against the customer's own defect-density measurements, with the published activation energies shipping as defaults. The deliverable is a per-seat subscription to the calculator plus a one-time calibration report — deliberately a planning aid, not a full crystal-growth simulator.

Why now

Paper [0] supplies mechanism-resolved kinetics for the 3C→6H polytypic transition in SiC: fast nucleation of stacking faults with Ea = 1.5 eV and slow expansion of partial dislocations with Ea = 0.54 eV. The near-3× gap between the two activation energies is exactly the decomposition an Arrhenius planner needs — nucleation is far more temperature-sensitive than expansion, so safe anneal windows can be computed rather than found by trial-and-error. Because these are single-study, lab-derived values, the product is sized as a calculator seeded with them (with user calibration), not a deployed growth simulator — matching the evidence's readiness level.

Written by GLM · 13 Oct 2026

AI assessment

Backed by 1 paper80

A highly focused, low-complexity calculator that translates specific kinetic data into a practical process window for SiC engineers, though it suffers from low novelty due to a nearly identical existing idea.

Evidence strength
4/5
The idea directly utilizes specific activation energy values (1.5 eV and 0.54 eV) from the research to drive its calculations, matching the lab-scale evidence to a planning tool rather than an over-ambitious simulator.
Market pull
4/5
The named beneficiaries are the primary global players in SiC power electronics who face significant yield challenges related to polytype stability during high-temperature processing.
Novelty & moat
2/5
The idea is essentially a specific implementation of 'Barrier-to-Anneal', which already covers activation-energy prediction for the same 3C-to-6H transition and the same user persona.
Feasibility
5/5
Building a web-based Arrhenius calculator is a trivial software task that can be prototyped in days given the provided kinetic constants.
Wedge clarity
5/5
The wedge is extremely sharp: a single-purpose calculator for a specific polytypic transition in a specific material.
Simplicity / focus
5/5
The product avoids 'platform' creep, focusing exclusively on a kinetics calculator and a calibration report.

Scored by Gemma 4 · 13 Oct 2026. Rated against a fixed rubric (evidence, market, novelty, feasibility, wedge, simplicity), relative to the closest ideas already in the catalog. A prior estimate to compare ideas before real-world signal arrives.

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Who benefits

  • Wolfspeedcompany

    The largest merchant SiC substrate and epiwafer supplier runs boule growth and high-temperature processing where 3C inclusions and stacking faults destroy yield; a kinetics-based anneal-window calculator maps directly onto that process-control problem.

  • STMicroelectronicscompany

    A high-volume SiC MOSFET maker for automotive customers performs anneal steps where polytype and stacking-fault changes risk device yield; a quantitative dwell-time limit would tighten its internal process specifications.

  • ROHM Semiconductorcompany

    ROHM (with its SiCrystal substrate subsidiary) qualifies internal anneal processes for SiC devices; a cheap calculator that de-risks schedules before wafer commits fits its yield-qualification workflow.

  • onsemicompany

    As onsemi ramps SiC diode and MOSFET production, an evidence-based anneal-window planner reduces the experimental iterations needed to qualify high-temperature steps.

Research it builds on

  1. Global Journal For Research Analysis
    2025 · 108 citations
    All ideas from this paper →
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feasibility